In semiconductor integrated circuits of recent years, as the level of integration increases due to miniaturization, the scale of the system mounted on a one-chip semiconductor integrated circuit has increased and so has its operation speed. Further, regarding the application field of semiconductor integrated circuits, markets for mobile telephones, digital cameras, and PDAs are rapidly growing. In the application field of such mobile devices, a power saving ability is a big added value for products. The capacity of semiconductor integrated circuits for memory storage increases every year and the need for power saving technology has become a big issue. Particularly, the reduction of the charge/discharge current of digit lines, which is the main element in the consumption current, has become an important issue in SRAM technology.
FIG. 6 is a complete block diagram of a conventional SRAM semiconductor memory device, described in Patent Document 1, in which the charge/discharge current of digit lines is reduced. The semiconductor memory device in FIG. 6 is constituted by n+1 (bit) memory blocks 100-1 to 100-(n+1). Each memory block is constituted by i+1 columns 0 to i and is accessed by specifying an address using m+1 word lines 0 to m, therefore the device has [(m+1)×(i+1)]word×(n+1)bit (digit) configuration as a whole. Further, corresponding to this configuration, a precharge decoder 101, a word line decoder 102, and a column decoder 103 are provided.
Further, for each memory block, memory cells 105 arranged in (m+1) by (i+1) arrays, a precharge circuit 104 provided for each digit line pair, a column selector 107, a sense amplifier 108, and a write buffer 109 are provided.
Further, one of the characteristics of the configuration in FIG. 6 is that column selection lines (inverted logic) SB[0:i], which are inverted signals of column selection lines (positive logic) S[0:i], are wired to each memory cell 105. The device is configured such that digit line pairs other than selected digit line pairs are not connected to the memory cells 105 because of these column selection lines (inverted logic) SB[0:i].
FIG. 7 is a block diagram showing the internal configuration of the memory cell 105 of the conventional semiconductor memory device shown in FIG. 6. The memory cell 105 is constituted by inverters INV1 and INV2 constituting a latch, access transistors Tr1 and Tr2, and transistors Tr3 and Tr4 that set the gate potential of the access transistors Tr1 and Tr2 to the potential of the word line WL or “Lo” using the column selection line (inverted logic) SB.
Further, the transistor Tr3 is constituted by a P-channel MOS transistor having its gate connected to the column selection line (inverted logic) SB, its source connected to the word line, and its drain connected to gates of the access transistors Tr1 and Tr2. Meanwhile the transistor Tr4 is constituted by a N-channel MOS transistor having its gate connected to the column selection line (inverted logic) SB, its drain connected to the gates of the access transistors Tr1 and Tr2, and its drain grounded.
By configuring the memory cell 105 as described above, when the column selection line (inverted logic) SB is at a low level, the transistor Tr3 is turned on and the transistor Tr4 is turned off. As a result, the gates of the access transistors Tr1 and Tr2 are connected to the word line WL. Meanwhile, when the column selection line (inverted logic) SB is at a high level, the transistor Tr3 is turned off and the transistor Tr4 is turned on. As a result, the gate potentials of the access transistors Tr1 and Tr2 are pulled down to a low level. As described, the column selection line (inverted logic) SB at the high level is connected to the SRAM cell connected to non-selected digit line pair, and readout of held data is not performed on the digit line pair.
FIG. 8 is a timing chart for explaining the operation of the conventional semiconductor memory device shown in FIGS. 6 and 7 for one cycle of an input clock signal CLK. Here, it is assumed that a selected word line and a selected column digit line pair are WL[0] and D [0]/DB [0]. The device operates identically when other word lines and other column digit line pairs are selected. When the clock signal CLK changes from a low level to a high level, a precharge line PC becomes a low level and the precharge of each digit line pair is completed. Further, when the clock signal CLK changes to the high level, the column selection line (positive logic) S[0] and the world line (positive logic) WL[0] go to a high level. When the column selection line (positive logic) S[0] goes to the high level, the column digit line pair D[0]/DB[0] is connected to the sense amplifier 108 and the write buffer 109 via the column selector 107.
Further, because of the fact that the column selection line (positive logic) S[0] goes to the high level, only SB[0] out of the column selection lines (inverted logic) goes to a low level and is fed to the SRAM cell connected to the digit line pair D[0]/DB[0]. Because of this, the transistor Tr3 is turned on and the transistor Tr4 is turned off inside the SRAM cell connected to the word line WL[0] and the digit line pair D[0]/DB[0], and a potential difference corresponding to data held by the latch portion constituted by the inverters INV1 and INV2 occurs only between the digit line pair D[0]/DB[0].
Then, when low-level data is held at a node A of the latch portion, a cell current Id of the memory cell 105 flows from the digit line D to the ground via the transistor Tr1 and the inverter INV2. Meanwhile, when high-level data is held at a node B of the latch portion, a cell current Idb of the memory cell 105 flows from the power supply of the inverter INV1 to the digit line DB via an output terminal of the inverter INV1 and the transistor Tr2.
Further, the other digit line pairs [1:i]/DB[1:i] maintain a digit line potential Vpc, which is approximately the potential at the time of precharging, since data is not read from these line pairs. As a result, a potential difference corresponding to the held data in the digit line pair D[0]/DB[0] occurs only in the SRAM cell connected to the word line WL0 and the column selection line S[0] and is outputted as an output data DOUT[0:n] via the sense amplifier 108.
Then, when the clock signal CLK changes from the high level to the low level, the precharge line PC goes to a high level, and the column selection line S[0] and the word line WL[0] go to a low level. Because of the fact that the precharge line PC goes to the high level, precharging of each digit line pair starts. At this time, the digit line pairs D[0:i]/DB[0:i] are charged so that a potential difference between each digit line pair is equal to each other and is the predetermined digit line precharge potential Vpc. However, since the other digit line pairs D[1:i]/DB[1:i] maintain the digit line precharge potential Vpc, these digit line pairs are hardly charged at the time of precharging. Because of the fact that the column selection line (positive logic) S[0] goes to the low level, the column selection line (inverted logic) SB[0] goes to a high level and is fed to the SRAM cell, along with the other column selection lines (inverted logic) SB[1:i] maintaining the high level. As a result, the transistors Tr3 are turned off and the transistors Tr4 are turned on inside all the memory cells 105, and data is not read from the digit line pairs D[0:i]/DB[0:i].
Further, a technology similar to that of Patent Document 1 is described in Patent Document 2.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2000-339971A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-60-247892